This invention relates to a method of manufacturing an integrated semiconductor device in which at least one transistor for high power (hereinafter referred to as "a power transistor" when applicable) and a plurality of transistors for small signals (hereinafter referred to as "small signal transistors" when applicable) are formed on the same semiconductor substrate.
To appreciate a full understanding of the merits of this invention, first a conventional method of manufacturing an integrated semiconductor device will be described with reference to FIG. 1 which shows the structure of a conventional semiconductor device having three NPN transistors formed on a P+ type semiconductor substrate.
N+ type floating collector regions 2 are first formed in discrete regions of a P+ type semiconductor substrate 1 by selective diffusion. Then, an N- type layer is formed thereon by epitaxial growth.
Thereafter, in order to isolate transistors from one another, P+ type isolating regions 4 are formed so that each of regions 4 contacts with the surface of the P+ type semiconductor substrate 1. Next, N+ type collector-walls 5 contacting the floating collector regions 2 are respectively formed by diffusion. Thereafter P+ type base regions 6 and N+ type emitter region 7 are formed in succession by diffusion in the N- type epitaxial collector regions 3. Finally, collector electrodes 9, base electrodes 10, emitter electrodes 11, and ground electrode 12 of the P+ type semiconductor substrate are suitably formed.
This prior art structure is disclosed by Davis, in "Bipolar Design Considerations for the Automotive Environment" pp. 419-427 of IEEE Journal of solid-state circuits, vol. SC-8. No. 6, December 1973. As discussed therein, the so-called "Parasitic lateral n-p-n transistor" is formed as shown in FIG. 7 of that article. In such a device a serious problem exists with negative voltage transients applied to the N- epitaxial layer that forward bias the N/P substrate and junction to inject electrons into the substrate. Given these structural difficulties, the prior art recognizes the practice of connecting the N- epi islands to a positive supply terminal for suitable biasing. This technique and others disclosed in the article are employed to prevent parastic collection of substrate injected electrons.
Also, with the conventional semiconductor device having the above-described structure, it is however impossible to make the N- type epitaxial collector region 3 sufficiently thick. Therefore, it is difficult to provide transistors having high breakdown voltage by this conventional method. Since the collectors are provided in the upper surface of the substrate by means of the N+ type collector-walls 5, the effective areas of the collectors are reduced. Thus, it is also difficult to provide transistors capable of handling a large electric current by this conventional method.